Octatrack base: skip the stock time-stretch analysis on tracks with TSTR OFF - #975

What changes

Stock OS 1.40C runs a time-stretch helper task (entry 0x40098a5c, prio 1). The frame interrupt wakes it every frame, and it runs a splice search (0x4009871c) and a transient detector (0x400985ac) for every playing Flex or Static track, whatever the track's TSTR. While any detector call still has samples left, the task loops again without sleeping.

The engine reads the splice result only when the voice's resolved TSTR (voice +24) is not OFF, at 0x40008252 and 0x40008a1c. It reads the transient markers only in BEAT, at 0x400082a8. The trig routine only writes reset requests into the marker block (0x4000f57e, 0x4000f830) and bumps the splice request (voice +144).

The base now hooks 0x40098b2c (8 bytes, mw_ts_gate in status.s). On a track whose resolved TSTR is OFF it skips both stages and moves on to the next track. Every other track runs the stock instructions it displaced. Pending reset requests stay pending, so the first pass after TSTR goes back on catches up, as stock does after a jump. It writes nothing in the task's SRAM (0x80006924..0x80007873).

Bryan T measured the task's cost on hardware, and Zac Kyoti mapped it (reference/kb/memory-map.md, "Timestretch: the helper task"). Upstream octabam only documents it.

The beta base is regenerated (identity 5273cecd…, .bin 239ca990…; browser and build_core.py builds byte-identical). The bound packages are relinked: their bytes are unchanged, and only requiredBase moves. Before building, clean main reproduced its committed base (e5052495…).

Also in this PR, a fix found on the way: sdk/tests/test_table_admission.py failed wherever an m68k compiler is installed. Since the Beat Slicer merge, machine_admission_runtime.c needs sdk/machines/octatrack/include and sample_editor_actions.c. CI skips the test without that compiler, so main looked green.

Evidence

Hardware (owner's MKII, 27 Oct 2026). Two --dev twins were RAM-booted, both with the beta's loader flags but without the resident controllers: one from main (a79a3fe8…), one from this branch (a0cf1a04…). Same project and Part, Flex track 4 playing STAB_04 on A01 at 119 BPM, SRC SETUP open throughout. Each figure is the mean of eight stats readings 2.5 s apart (CPU, per mille):

• That is about 16‰ per playing track with TSTR OFF, and no change with time-stretch on.
• With OFF on the branch twin, track 4's marker block (0x80003d48) stayed frozen.
• Turned to BEAT, the ring index advanced and new markers appeared within about a second.
• The voice's resolved TSTR (0x80004be8) read 0 and 3 as expected.

Not tested:

• The committed beta base itself (5273cecd) on a unit. The twins differ from it in --dev and in the resident controllers.
• Eight tracks at once.
• AUTO and NORM by ear.
• Recorder loops (PICKUP never resolves to OFF, so the gate doesn't apply to them).

Checks: npm run pr:ready Ready. modules:compat reports 0 problems. sdk:check passes, including the fixed admission test.

Coordination

This changes the committed base. Any other open base change (today's SRC SETUP base fix for #972, #943) needs a rebuild after whichever merges first. The owner wants one base per round, so this can also be folded into that base.

What the guides lacked

docs/OCTATRACK_DRIVING.md: SRC SETUP's TSTR on encoder E moved only after a large turn (encE+40; seven encE+2 steps did nothing). Added to the encoder row there.

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